In the previous post “Interfaces for 40 GbE Architecture in Data Centers I”, we generally learned about the Chip-to-chip port side interface in the 40 Gigabit Ethernet architecture. And in this post, we will continue to learn the interfaces used for 40 Gigabit Ethernet. This article will focuses on the Chip-to-module direct attach interface.
A chip-to-module interface consists of a short PCB trace and a module connector between a port side IC and a module that is without retiming capability.
To increase the port densities to achieve the higher required bandwidth in chassis, the signal conditioning function was moved from inside of a 10 Gigabit pluggable module, such as XFI, to the port side interfaces. As a result, a new high-speed 10 GE serial electrical interface called SerDes Framer Interface (SFI) was defined by SFF MSA. SFI is applied for an interface between a host ASIC and the small form-factor pluggable module, SFP+ (the follwing picture shows the connection methods).
SFI is defined for both limiting and linear mode modules. In the limiting mode, SFI supports PHY connections to the limiting SFP+ optical transceivers, such as 10GBASE-SR optics (MMF 300m), 10GBASE-LR optics (SMF 10km), and 10GBASE-ER optics (SMF 40km). In the linear SPI interface, stronger signal conditioning capabilities are required to compensate for electrical dispersion. The linear SPI interface can be used with 10GBASE-LRM optics, and also the passive Direct Attach Cable (DAC) in the length from 1m to 7m, such as QSFP-H40G-CU5M DAC and EX-QSFP-40GE-DAC-50CM DAC.
To improve the port side densities in a chassis, the new XLPPI (40 Gbps Parallel Physical Interface) electrical specification was defined by IEEE 802.3. Another reason for the development of XLPPI is to address the incompatibility between the XLAUI and the QSFP+ module. Therefore, XLPPI is an interface with high port-density, supporting a direct connection to a Quad Small Form Factor Pluggable (QSFP or QSFP+) module (e.g. Brocade QSFP+ and Finisar QSFP+) without the necessity of a re-timer function.
Compared with XLAUI interfaces, XLPPI Interface is defined in 802.3ba Annex 86a as the interface between the PMA and PMD functions (where as the XLAUI dissects the PMA). The XLPPI is derived from the SFI interface and places higher signal integrity requirements on the host PMA than the XFI based XLAUI.
XLPPI is the electrical specification to both passive copper based 40GBASE-CR4 QSFP+ module and the optical modules such as the short reach QSFP-40G-SR4 optical transceiver and QSFP-40G-LR4 optical transceiver. Therefore, currently QSFP+ modules with XLPPI interfaces support 40GBase-CR4 (both passive and active) cables and 40GBase-SR4 (either AOC or using the MPO/MTP connector) cables.